PDK Engineer (DRC/LVS Rule Coding)

AGG-J-019 · Semiconductor · In Japan

What you will do

Develop the process design kit (PDK) for semiconductor design. Write DRC, LVS, FILL and PERC rule decks in Siemens Calibre, Synopsys IC Validator (ICV) and Cadence Pegasus, and build parameterized cells (pcells in Cadence Virtuoso, PyCells in Synopsys Custom Compiler). Team-based work with on-the-job training. The team wants people who can start soon.

You need

About 3 years of experience, including writing rule decks from scratch for at least one of the tasks above (DRC, LVS, FILL or PERC in Calibre, ICV or Pegasus, or pcell/PyCell development). Intermediate Excel.

Language

Japanese: not required if your experience and skills match. English: enough to read and understand EDA vendor tool manuals.

Who can apply

This job is only for people who live in Japan now, for example as a student or with a work visa. Every job is in Japan.

Employment

Dispatch via AGG (AGG employs you)

Work style

On-site office work, no cleanroom and no remote work. Day shift on weekdays, weekends off. Some overtime (about 20–30 hours a month).

Salary

Shared at your first consultation

Hiring organization: Fukuyoshi Inc.

Last updated: 2026-10-30. The work location and the company name are given in writing at your first consultation. AGG (Fukuyoshi Inc.) charges candidates no fees.

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